1. Field of the Invention
The present invention relates generally to analog-to-digital converters, and more specifically, to an on-chip system including a delta-sigma analog-to-digital converter (ADC) that is operated intermittently while the remainder of the system is halted to reduce noise.
2. Background of the Invention
System-on-Chip (SoC) integrated circuits are ubiquitous in embedded applications such as household devices, personal computers and industrial electronics. SoCs reduce the cost of systems and increase their performance by reducing the parts count and decreasing the number of interconnects required to implement a given device. SoCs frequently include analog conversion components such as ADCs and digital-to-analog converters (DACs) in order to provide a system interface to analog signals, perform analog measurements and to provide analog outputs.
Delta-sigma modulator based analog-to-digital converters (ADCs) are in widespread use and are particularly desirable for use in SoC circuits. SoC circuit are typically either entirely digital or are mixed-signal with some analog circuits, but having at least one large-scale digital logic block, such as a processor core. Delta-sigma modulator based ADCs typically have relatively low analog circuit performance requirements and small analog circuit area. Therefore, they are ideal for mixed-signal circuits in which analog and digital signals and components coexist.
The delta-sigma modulator based ADC typically includes an analog loop filter that receives an input signal and a quantizer that converts the analog output of the loop filter to a digital representation. A feedback signal provided from the output of the quantizer is introduced to the analog loop filter to close the loop such that the average output of the quantizer is equal to the value of the input signal. The output of the quantizer is then filtered by a low-pass digital filter having a large number of taps, in order to provide an accurate conversion result from the quantizer output, which typically includes thousands of values per conversion cycle.
Since the operation of the delta-sigma modulator based ADC as described above is a quasi-continuous process within both the loop filter and the digital low-pass filter at the output, delta-sigma modulator based ADCs are typically operated continuously, unlike so-called “flash” ADCs or successive-approximation ADCs, which can be used to acquire a single sample and then be shut down between sampling/conversion cycles. Interrupting the operation of the converter between samples will cause disruption of the operation of the analog loop filter. Therefore delta-sigma modulator based ADCs are typically designed to operate continuously producing a sample value at the end of a period corresponding to the sampling rate.
In an SoC design, the ADC typically coexists with a large amount of digital logic, which typically implements a processor core or a dedicated signal processing circuit. Such circuits generate a large amount of switching noise on power supply rails of the integrated circuit, as well as generating noise on signal lines within the ADC portion of the integrated circuit that affect the converter output values. The noise level at the ADC input affects the useful resolution of the converter and is typically manageable only by adjusting the circuit layout and “managing” the timing of the digital switching signals so that all of the transitions occur over a small portion of the ADC conversion cycle. The highest frequency digital circuit clocks are typically the signals that are managed, as those clocks are responsible for the majority of the noise generated in the analog circuits.
However, digital circuits that are operated with an asynchronous clock with respect to the converter clock, and those that have some level of asynchronous operation, such as processors, which are affected by program flow as well as clock state cannot be managed in the manner described above, as logic transitions can and will occur at any point in the ADC conversion cycle. Further, when a processor core instruction rate is much higher than the converter sample rate, the various phases of instruction processing will lie throughout the conversion cycle and cannot be held to just a small window without affecting performance of the core.
Therefore, it would be desirable to provide an SoC including a delta-sigma ADC that can be operated in a manner that reduces or eliminates the noise generated in during analog signal conversions by a processor core or other digital circuit.